Digital test instruments apply test stimuli to and collect test responses from units under test (UUTs) across several channels simultaneously during the execution of a functional digital test. A typical digital functional test includes a sequence of patterns. Each pattern includes specifications of the test stimulus to apply and/or test response to collect, as well as the timing for those actions.
Digital test instruments typically provide a way to compare collected test responses with expected responses and to produce for each channel in the instrument a pass or fail test result that indicates whether the actual response matches the expected response for that channel on a particular pattern. The individual channel results on a pattern are logically combined to produce an overall test result for that pattern. Pattern results, in turn, are logically combined to produce an overall test result for the complete test.
A digital test instrument may include a hardware component called a pattern controller that determines the particular sequence of patterns executed during a digital test. In such an instrument, the instructions for generating test stimuli and/or collecting test responses are stored in pattern memory and the instructions for a particular pattern are found at a particular address within that memory. The pattern controller generates the sequence of test patterns for a test by controlling the sequence of addresses applied to the pattern memory. In a simple test, the pattern controller can produce a linear sequence of patterns by incrementing the pattern memory address. In more complicated tests, the pattern controller may produce sequences of pattern memory addresses that skip over certain patterns, or may cause groups of patterns to execute several times during the execution of a test.
Normally, pattern results are simply stored in the digital test instrument hardware during test execution, and retrieved after the test has completed execution to provide diagnostic information to help isolate and diagnose faults on a UUT. However, digital test instruments may also use pattern results to dynamically alter the sequence of patterns executed in a test. To accomplish this, the test instrument is typically designed so that on a particular pattern the pattern controller can take one of two actions based on the setting of the overall test result for the pattern.
The delay between the time when the test pattern is applied to the unit under test and the time when the result of the test pattern is applied to the pattern controller is termed the pass/fail results latency, or simply the results latency. In high speed test instruments that rely on pipelining techniques to achieve their high speed performance, this latency is usually expressed in terms of a number of patterns. The user of the digital test instrument must account for this latency when writing a test program that runs on the instrument and uses its conditional execution capability.
As an example, consider a test application, shown in FIGS. 1A and 1B, in which a digital test instrument with a results latency of four patterns is used to detect when a synchronous counter 10 reaches the zero state on its outputs. Patterns 1-5 form a conditional loop that clocks the counter once per loop iteration and exits when the counter outputs are all low.
Digital functional test programs are expensive to develop, and once validated and deployed, there can be a tremendous reluctance to modify them. Such test programs can last for many years, and can easily outlast the test equipment on which the test programs were originally designed to run. When such a test program is migrated to a new test system with different digital test instruments, the new digital test instruments should provide the same results latency as that of the original digital test instruments.
However, as a general trend, the maximum speed of digital test instruments has increased over time. Higher operating speeds mean more pipeline stages, and a higher results latency. This increased latency can “break” working test programs.
FIG. 2 is an execution trace example that illustrates operation of the test program of FIG. 1B on a first digital test instrument having a results latency of four pattern cycles. As shown in FIG. 2, the test program runs properly on the first digital test instrument.
FIG. 3 is an execution trace example that illustrates operation of the test program of FIG. 1B on a second digital test instrument having a results latency of nine pattern cycles. As shown in FIG. 3, the test program fails to run properly on the second digital test instrument.
As a result, there is a need for digital test instruments and test methods which overcome the problem of running existing test programs on digital test instruments which have different results latencies.